[ Quellcode: verilator ]
Paket: verilator (3.916-1build1)
Links für verilator
Trisquel-Ressourcen:
Quellcode-Paket verilator herunterladen:
Betreuer:
Original Maintainers:
- Debian Electronics Team (E-Mail-Archiv)
- أحمد المحمودي (Ahmed El-Mahmoudy)
Externe Ressourcen:
- Homepage [www.veripool.org]
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fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
Andere Pakete mit Bezug zu verilator
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- dep: libc6 (>= 2.14) [amd64]
- GNU C Library: Shared libraries
auch ein virtuelles Paket, bereitgestellt durch libc6-udeb
- dep: libc6 (>= 2.4) [i386]
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- dep: libgcc1 (>= 1:3.0) [amd64]
- GCC support library
- dep: libgcc1 (>= 1:4.2) [i386]
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer
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- sug: systemc
- Paket nicht verfügbar
verilator herunterladen
| Architektur | Paketgröße | Größe (installiert) | Dateien |
|---|---|---|---|
| amd64 | 2.811,0 kB | 12811 kB | [Liste der Dateien] |
| i386 | 2.902,7 kB | 11385 kB | [Liste der Dateien] |