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Paquet : iverilog (10.3-1build1)

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

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Télécharger iverilog

Télécharger pour toutes les architectures proposées
Architecture Taille du paquet Espace occupé une fois installé Fichiers
amd64 1 815,4 ko6394 ko [liste des fichiers]
armhf 1 590,2 ko4224 ko [liste des fichiers]