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Paket: verilator (4.028-1)

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

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verilator indir

Tüm mevcut mimariler için indir
Mimari Paket Boyutu Kurulu Boyut Dosyalar
amd64 4.419,3 kB19404 kB [dosya listesi]
armhf 3.610,8 kB12253 kB [dosya listesi]