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[ 原始碼: covered  ]

套件: covered (0.7.10-3build1)

covered 的相關超連結

covered

Trisquel 的資源:

下載原始碼套件 covered

維護者:

Original Maintainers:

  • Debian Electronics Team (郵件存檔)
  • أحمد المحمودي (Ahmed El-Mahmoudy)

外部的資源:

  • 主頁 [covered.sourceforge.net]

相似套件:

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

其他與 covered 有關的套件

  • 依賴
  • 推薦
  • 建議
  • dep: libc6 (>= 2.11) [i386]
    GNU C Library: Shared libraries
    同時作為一個虛擬套件由這些套件提供: libc6-udeb
    dep: libc6 (>= 2.14) [amd64]
  • dep: libtcl8.6 (>= 8.6.0)
    Tcl (the Tool Command Language) v8.6 - run-time library files
  • dep: libtk8.6 (>= 8.6.0)
    Tk toolkit for Tcl and X11 v8.6 - run-time files
  • dep: tklib
    standard Tk Library
  • dep: zlib1g (>= 1:1.1.4)
    compression library - runtime
  • rec: iverilog
    Icarus verilog compiler
    或者 verilog
    Icarus verilog compiler (transitional package)
    或者 gplcver (>= 2.12a-1.1)
    Verilog simulator

下載 covered

下載可用於所有硬體架構的
硬體架構 套件大小 安裝後大小 檔案
amd64 527.1 kB2375 kB [文件列表]
i386 533.6 kB2506 kB [文件列表]