[ 原始碼： verilator ]
套件： verilator (3.916-1build1)
verilator 的相關超連結
Trisquel 的資源：
下載原始碼套件 verilator：
維護者：
Original Maintainers:
- Debian Electronics Team (郵件存檔)
- أحمد المحمودي (Ahmed El-Mahmoudy)
外部的資源：
- 主頁 [www.veripool.org]
相似套件：
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
其他與 verilator 有關的套件
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- dep: libc6 (>= 2.14) [amd64]
- GNU C Library: Shared libraries
同時作為一個虛擬套件由這些套件提供： libc6-udeb
- dep: libc6 (>= 2.4) [i386]
-
- dep: libgcc1 (>= 1:3.0) [amd64]
- GCC support library
- dep: libgcc1 (>= 1:4.2) [i386]
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer
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- sug: systemc
- 套件暫時不可用