[ 原始碼： iverilog ]
套件： verilog (10.1-0.1build1)
verilog 的相關超連結
Trisquel 的資源：
下載原始碼套件 iverilog：
維護者：
Original Maintainers:
- Debian Electronics Team (郵件存檔)
- Hamish Moffatt
- Wesley J. Landaker
- Ramakrishnan Muthukrishnan
- أحمد المحمودي (Ahmed El-Mahmoudy)
外部的資源：
- 主頁 [iverilog.icarus.com]
相似套件：
Icarus verilog compiler (transitional package)
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
This is a dummy transitional package that will ensure a proper upgrade path. This package may be safely removed after upgrading.