套件： netgen-lvs (1.5.133-1)
netgen-lvs 的相關超連結
Trisquel 的資源：
下載原始碼套件 netgen-lvs：
維護者：
Original Maintainers:
- Debian Electronics Team (郵件存檔)
- Ruben Undheim
外部的資源：
- 主頁 [opencircuitdesign.com]
相似套件：
Netlist comparison - Layout vs Schematic (LVS)
Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit.
Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time.
Note that the executable name in Debian is 'netgen-lvs'. For details, see /usr/share/doc/netgen-lvs/README.Debian
其他與 netgen-lvs 有關的套件
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- dep: libc6 (>= 2.29)
- GNU C Library: Shared libraries
同時作為一個虛擬套件由這些套件提供： libc6-udeb
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: python3-tk
- Tkinter - Writing Tk applications with Python 3.x