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[ 原始碼: opensta  ]

套件: opensta (0~20191111gitc018cb2+dfsg-1build1)

Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

其他與 opensta 有關的套件

  • 依賴
  • 推薦
  • 建議
  • dep: libc6 (>= 2.29)
    GNU C Library: Shared libraries
    同時作為一個虛擬套件由這些套件提供: libc6-udeb
  • dep: libgcc-s1 (>= 3.0) [amd64]
    GCC support library
    dep: libgcc-s1 (>= 3.5) [armhf]
  • dep: libreadline8 (>= 6.0)
    GNU readline and history libraries, run-time libraries
  • dep: libstdc++6 (>= 6)
    GNU Standard C++ Library v3
  • dep: libtcl8.6 (>= 8.6.0)
    Tcl (the Tool Command Language) v8.6 - run-time library files
  • dep: zlib1g (>= 1:1.1.4)
    compression library - runtime

下載 opensta

下載可用於所有硬體架構的
硬體架構 套件大小 安裝後大小 檔案
amd64 791.6 kB3782 kB [文件列表]
armhf 644.6 kB2479 kB [文件列表]